Gate stack optimization to minimize power consumption in super-lattice FETs

In this work the effect of high-k gate dielectrics on the power-speed performance of SL-FETs realized with the InGaAs/InAlAs and InGaAs/InP material pairs is investigated by numerical simulations. The analysis shows that the InGaAs/InP pair, in association with Al2O3 as the gate dielectric, provides the most promising results for high-performance applications, i.e. an on-state current approaching 2 mA/μm and an intrinsic delay lower than 0.16 ps at a supply voltage of 0.4 V. The average subthreshold swing SS is much lower than 60 mV/dec over six current decades and the point slope SS ≈ 20mV/dec. These results outperform the ITRS requirements projected to year 2022 in terms of both static and dynamic power dissipation, and make the proposed device well suited for high-performance and low-power applications at the same time.