Effects of the low-field mobility in single-gate and double-gate ultrathin-body MOSFETs scaled to the ultimate technology nodes

In this work we investigate the performance of fully-depleted silicon-on-insulator (SOI) and double-gate (DG) FETs at their extreme miniaturization limits. The model fully accounts for quantum confinement effects; current transport is simulated by an improved density-gradient approach supported by a new thickness-dependent mobility model which nicely fits available measurements. The simple rule resulting from this investigation is that stringent short-channel effect constraints can be fulfilled with Lg/tSi ≈ 5 for the SOI-FET and Lg/tSi ≈ 2 for the DG-FET. The effects of the degradation of the low-field mobility and the roll-off of the threshold voltage due to the scaling-down of the silicon thickness are shown down to tSi= 1 nm.