In this work we investigate the performance of double-gate (DG) and cylindrical nanowire (CNW) FETs at their extreme miniaturiza-tion limits. The model fully accounts for quantum electrostatics; cur-rent transport is simulated by an improved density-gradient approach supported by a new thickness-dependent mobility model which nicely fits available measurements for both SiO2 and HfO2 gate di-electrics. The performance comparison between SiO2 and HfO2 FETs with the same EOT demonstrates that the latter provides an improved on-current due to lateral capacitive effects despite the low-field mobility degradation.

Effects of high-κ (HfO) gate dielectric in double-gate and cylindrical-nanowire MOSFETs scaled to the ultimate technology nodes / E. Gnani; S. Reggiani; M. Rudan; G. Baccarani. - STAMPA. - 11:(2006), pp. 121-122. (Intervento presentato al convegno IEEE 2006 Silicon Nanoelectronics Workshop tenutosi a Honolulu, Hawaii nel 11-12 June 2006).

Effects of high-κ (HfO) gate dielectric in double-gate and cylindrical-nanowire MOSFETs scaled to the ultimate technology nodes

GNANI, ELENA;REGGIANI, SUSANNA;RUDAN, MASSIMO;BACCARANI, GIORGIO
2006

Abstract

In this work we investigate the performance of double-gate (DG) and cylindrical nanowire (CNW) FETs at their extreme miniaturiza-tion limits. The model fully accounts for quantum electrostatics; cur-rent transport is simulated by an improved density-gradient approach supported by a new thickness-dependent mobility model which nicely fits available measurements for both SiO2 and HfO2 gate di-electrics. The performance comparison between SiO2 and HfO2 FETs with the same EOT demonstrates that the latter provides an improved on-current due to lateral capacitive effects despite the low-field mobility degradation.
2006
IEEE 2006 Silicon Nanoelectronics Workshop
121
122
Effects of high-κ (HfO) gate dielectric in double-gate and cylindrical-nanowire MOSFETs scaled to the ultimate technology nodes / E. Gnani; S. Reggiani; M. Rudan; G. Baccarani. - STAMPA. - 11:(2006), pp. 121-122. (Intervento presentato al convegno IEEE 2006 Silicon Nanoelectronics Workshop tenutosi a Honolulu, Hawaii nel 11-12 June 2006).
E. Gnani; S. Reggiani; M. Rudan; G. Baccarani
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/28844
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