Investigating the performance limits of silicon-nanowire and carbon-nanotube FETs

In this work we investigate and compare the electrostatics of fully depleted cylindrical silicon-nanowire (SiCNW) FETs, four-gate rectangular nanowire (4G RNW) FETs, tri-gate rectangular nanowire (3G RNW) FETs and gate-all-around carbon-nanotube (GAA-CNT) FETs at advanced miniaturization limits. In doing so, we rigorously solve the coupled Schroedinger–Poisson equations within the device cross-sections and fully account for quantum-mechanical effects. The investigation, carried out for the 65 and 45 nm technology nodes, leads to the unexpected conclusion that, for an assigned threshold voltage, the gate-all-around CNT-FET offers only a slightly better performance with respect to the SiCNW and the 4G RNW-FETs. This is due to the compensation of two different mechanisms, namely a higher gate efectiveness and a lower density of states. The 3G RNW yields instead an electron density within the channel which is about 25% lower than the SiCNW and 4G RNW-FETs at a given gate voltage. Such a reduced performance is due to its inherent asymmetry, which negatively affects the gate control on the channel charge.