Drain-conductance optimization in nanowire TFETs

In this work we examine the problem of the nonlinear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic operation and severely degrades the device dynamic properties compared with standard CMOS FETs. The problem is investigated with the help of an analytical model which highlights the constraints of the device design by splitting the effects of the tunneling probability from the density of states in the source, channel and drain, and makes it possible to design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions. So doing, we remove the above characteristics’ feature and recover a large drain conductance without degrading the subthreshold slope. The optimized device is numerically simulated using the k·p model, whose results are in fair agreement with the analytical one.