Physical Model of the Junctionless UTB SOI-FET

In this paper, we model the electrical properties of a junctionless (JL) ultrathin-body silicon-on-insulator field-effect transistor (SOI-FET), which has been proposed as a possible alternative to the junction-based SOI-FET. The model is based on improved depletion approximation, which provides a very accurate solution of Poisson’s equation and allows for the computation of the substrate, as well as the Si-body lower- and upper-surface potentials by an iterative procedure, which accounts for the backoxide (BOX) charge and thickness and the potential drop within the substrate. The drain current is then computed versus gate, drain, and substrate voltages via integral expression and validated by comparison with technology computer-aided design simulation results. Analytical models of the field-effect-transistor threshold voltage and subthreshold slope are worked out against the substrate voltage, highlighting the effect of the substrate doping and BOX thickness on the aforementioned parameters. In essence, this work provides the physical background for better understanding of the JL SOI-FET and its assessment for logic applications.