In this work we investigate the electrostatics of the silicon-based Pi-gate FET and the top-gate carbon-nanotube FET at extreme miniaturization limits. In order to do so, we solve the coupled Schroedinger-Poisson equations within the two device cross sections, and compare the channel-charge and capacitance curves as functions of the gate voltage. This study shows that, for a fixed cross-sectional area, the quantitative differences between the two devices are small both in terms of charge and capacitance. The use of a classical model for the $Pi$-gate FET shows instead that the resulting discrepancies with respect to the quantum-mechanical (QM) model are very relevant using both the Boltzmann and Fermi statistics. Thus, accounting for quantum-mechanical effects is essential for a realistic prediction of the device on-current and transconductance at the feature sizes here considered. The effect of high-k dielectrics is also addressed. As opposed to planar-gate devices, the electrostatic performance of Si-nanowire and CNT-FETs is not adversely affected by the use of different insulating materials with the same equivalent oxide thickness. As a consequence, not only do high-$kappa$ dielectrics relieve the gate leakage problem; they also improve the device performance in terms of the gate-control effectiveness over the channel.

Quantum-mechanical analysis of the electrostatics in silicon-nanowire and carbon-nanotube FETs

GNANI, ELENA;MARCHI, ALEX;REGGIANI, SUSANNA;RUDAN, MASSIMO;BACCARANI, GIORGIO
2005

Abstract

In this work we investigate the electrostatics of the silicon-based Pi-gate FET and the top-gate carbon-nanotube FET at extreme miniaturization limits. In order to do so, we solve the coupled Schroedinger-Poisson equations within the two device cross sections, and compare the channel-charge and capacitance curves as functions of the gate voltage. This study shows that, for a fixed cross-sectional area, the quantitative differences between the two devices are small both in terms of charge and capacitance. The use of a classical model for the $Pi$-gate FET shows instead that the resulting discrepancies with respect to the quantum-mechanical (QM) model are very relevant using both the Boltzmann and Fermi statistics. Thus, accounting for quantum-mechanical effects is essential for a realistic prediction of the device on-current and transconductance at the feature sizes here considered. The effect of high-k dielectrics is also addressed. As opposed to planar-gate devices, the electrostatic performance of Si-nanowire and CNT-FETs is not adversely affected by the use of different insulating materials with the same equivalent oxide thickness. As a consequence, not only do high-$kappa$ dielectrics relieve the gate leakage problem; they also improve the device performance in terms of the gate-control effectiveness over the channel.
Proceedings of the European Solid-State Device Research Conference (ESSDERC 2005)
161
164
E. Gnani; A. Marchi; S. Reggiani; M. Rudan; G. Baccarani
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/11126
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