In this work we investigate by numerical simulation the electrical properties of the junctionless nanowire field-effect transistor, which has recently been proposed as a possible alternative to the junction-based FET. The numerical model assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior by highlighting the features of the I-V and C-V characteristics, as well as the electric potential and carrier concentration within the channel. Numerical results are compared with the experimental turn-on characteristics and are found to provide a generally-good agreement. Finally, we discuss the strengths and the limitations of this device as a possible candidate for future technology nodes.

Numerical Investigation on the Junctionless Nanowire FET / E. Gnani; A. Gnudi; S. Reggiani; G. Baccarani; N. Shen; N. Singh; G.Q. Lo; D.L. Kwong. - STAMPA. - (2011), pp. 1-4. (Intervento presentato al convegno 9th International Conference on Ultimate Integration of Silicon (ULIS 2011) tenutosi a Cork, Ireland nel 14-16 March) [10.1109/ULIS.2011.5757981].

Numerical Investigation on the Junctionless Nanowire FET

GNANI, ELENA;GNUDI, ANTONIO;REGGIANI, SUSANNA;BACCARANI, GIORGIO;
2011

Abstract

In this work we investigate by numerical simulation the electrical properties of the junctionless nanowire field-effect transistor, which has recently been proposed as a possible alternative to the junction-based FET. The numerical model assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior by highlighting the features of the I-V and C-V characteristics, as well as the electric potential and carrier concentration within the channel. Numerical results are compared with the experimental turn-on characteristics and are found to provide a generally-good agreement. Finally, we discuss the strengths and the limitations of this device as a possible candidate for future technology nodes.
2011
Proceedings of the 9th International Conference on Ultimate Integration of Silicon (ULIS 2011), pp. 1-4, Cork, 2011
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4
Numerical Investigation on the Junctionless Nanowire FET / E. Gnani; A. Gnudi; S. Reggiani; G. Baccarani; N. Shen; N. Singh; G.Q. Lo; D.L. Kwong. - STAMPA. - (2011), pp. 1-4. (Intervento presentato al convegno 9th International Conference on Ultimate Integration of Silicon (ULIS 2011) tenutosi a Cork, Ireland nel 14-16 March) [10.1109/ULIS.2011.5757981].
E. Gnani; A. Gnudi; S. Reggiani; G. Baccarani; N. Shen; N. Singh; G.Q. Lo; D.L. Kwong
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/103930
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