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Mostrati risultati da 21 a 40 di 55
Titolo Autore(i) Anno Periodico Editore Tipo File
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) Erfan Azarkhish;Igor Loi;Luca Benini 2013-01-01 - IEEE 4.01 Contributo in Atti di convegno -
Configurable Low-Latency Interconnect for Multi-core ClustersVLSI-SoC: From Algorithms to Circuits and System-on-Chip Design Giulia Beanato;Igor Loi;Giovanni De Micheli;Yusuf Leblebici;Luca Benini 2013-01-01 - Springer 2.01 Capitolo / saggio in libro -
A high-performance multiported L2 memory IP for scalable three-dimensional integration2013 IEEE International 3D Systems Integration Conference (3DIC) Erfan Azarkhish;Igor Loi;Luca Benini 2013-01-01 - 2013 IEEE Conference Proceedings 4.01 Contributo in Atti di convegno -
Energy-efficient vision on the PULP platform for ultra-low power parallel computing Conti, Francesco; Rossi, Davide; Pullini, Antonio; Loi, Igor; Benini, Luca 2014-01-01 - Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno -
Online process transformation for polyhedral process networks in shared-memory MPSoCs Meloni, Paolo; Tuveri, Giuseppe; Raffo, Luigi; Loi, Igor; Conti, Francesco 2014-01-01 - - 4.01 Contributo in Atti di convegno -
Energy efficient parallel computing on the PULP platform with support for OpenMP Rossi, Davide; Loi, Igor; Conti, Francesco.; Tagliavini, Giuseppe; Pullini, Antonio.; Marongiu, A...ndrea 2014-01-01 - IEEE 4.01 Contributo in Atti di convegno -
Ultra-low-latency lightweight dma for tightly coupled multi-core clusters Rossi, Davide; Loi, Igor; Haugou, Germain; Benini, Luca 2014-01-01 - Association for Computing Machinery 4.01 Contributo in Atti di convegno -
A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms Loi, Igor; Benini, Luca 2014-01-01 PROCEEDINGS - DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno -
A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse,... Philippe; Benini, Luca 2015-01-01 - Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno A −1.8V to 0.9V body bias, 60 GOPS-W 4-core cluster in low-power 28nm UTBB FD-SOI technology.pdf; A -1.8V to 0.9V Body Bias_Postprint..pdf
A Modular Shared L2 Memory Design for 3-D Integration Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca 2015-01-01 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS - 1.01 Articolo in rivista -
High Performance AXI-4.0 Based Interconnect for Extensible Smart Memory Cubes Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca 2015-01-01 - - 4.01 Contributo in Atti di convegno -
Exploring multi-banked shared-l1 program cache on ultra-low power, tightly coupled processor clusters Loi, Igor; Rossi, Davide; Haugou, Germain; Gautschi, Michael; Benini, Luca 2015-01-01 - Association for Computing Machinery, Inc 4.01 Contributo in Atti di convegno -
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision Conti, Francesco; Rossi, Davide; Pullini, Antonio; Loi, Igor; Benini, Luca 2016-01-01 JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY - 1.01 Articolo in rivista -
A 60 GOPS/W, -1.8 v to 0.9 v body bias ULP cluster in 28 nm UTBB FD-SOI technology Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, An...drea; Flatresse, Philippe; Benini, Luca 2016-01-01 SOLID-STATE ELECTRONICS - 1.01 Articolo in rivista -
On-the-fly adaptivity for process networks over shared-memory platforms Tuveri, Giuseppe; Meloni, Paolo; Palumbo, Francesca; Pietro Seu, Giovanni; Loi, Igor; Conti, Fran...cesco; Raffo, Luigi 2016-01-01 MICROPROCESSORS AND MICROSYSTEMS - 1.01 Articolo in rivista -
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision Pullini, Antonio; Conti, Francesco; Rossi, Davide; Loi, Igor; Gautschi, Michael; Benini, Luca 2016-01-01 - Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno -
PULP: A parallel ultra low power platform for next generation IoT applications Rossi, Davide; Conti, Francesco; Marongiu, Andrea; Pullini, Antonio; Loi, Igor; Gautschi, Michael...; Tagliavini, Giuseppe; Capotondi, Alessandro; Flatresse, Philippe; Benini, Luca 2016-01-01 - Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno -
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Ada...m; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca 2016-01-01 - Institute of Electrical and Electronics Engineers Inc. 4.01 Contributo in Atti di convegno -
Design and evaluation of a processing-in-memory architecture for the smart memory cube Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca 2016-01-01 - Springer Verlag 4.01 Contributo in Atti di convegno -
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA Meloni, Paolo; Deriu, Gianfranco; Conti, Francesco; Loi, Igor; Raffo, Luigi; Benini, Luca 2016-01-01 - ACM 4.01 Contributo in Atti di convegno -
Mostrati risultati da 21 a 40 di 55
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