A 4-core cluster fabricated in low power 28nm UTBB FD-SOI conventional well technology is presented. The SoC architecture enables the processors to operate 'on-demand' on a 0.44V (1.8MHz) to 1.2V (475MHz) supply voltage wide range and -1.2V to 0.9V body bias wide range achieving the peak energy efficiency of 60 GOPS/W, (419μW, 6.4MHz) at 0.5V with 0.5V forward body bias. The proposed SoC energy efficiency is 1.4x to 3.7x greater than other low-power processors with comparable performance.
A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology / Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse, Philippe; Benini, Luca. - STAMPA. - CFP15SOI-ART:(2015), pp. 7333483.1-7333483.3. (Intervento presentato al convegno IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 tenutosi a Rohnert Park, CA, USA nel 5-8 October 2015) [10.1109/S3S.2015.7333483].
A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
ROSSI, DAVIDE
;LOI, IGOR;BENINI, LUCA
2015
Abstract
A 4-core cluster fabricated in low power 28nm UTBB FD-SOI conventional well technology is presented. The SoC architecture enables the processors to operate 'on-demand' on a 0.44V (1.8MHz) to 1.2V (475MHz) supply voltage wide range and -1.2V to 0.9V body bias wide range achieving the peak energy efficiency of 60 GOPS/W, (419μW, 6.4MHz) at 0.5V with 0.5V forward body bias. The proposed SoC energy efficiency is 1.4x to 3.7x greater than other low-power processors with comparable performance.| File | Dimensione | Formato | |
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A −1.8V to 0.9V body bias, 60 GOPS-W 4-core cluster in low-power 28nm UTBB FD-SOI technology.pdf
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A -1.8V to 0.9V Body Bias_Postprint..pdf
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