Sfoglia per Autore
Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow
2007 I. Loi; F. Angiolini; L. Benini
Area and Power Modeling for Networks-on-Chip with Layout Awareness
2007 P. Meloni; I. Loi; F. Angiolini; S. Carta; M. Barbaro; L. Raffo; L. Benini
Developing Mesochronous Synchronizers to Enable 3D NoCs
2008 I. Loi; F. Angiolini; L. Benini
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
2008 Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L.
Synthesis of low-overhead configurable source routing tables for network interfaces
2009 Loi I.; Angiolini F.; Benini L.
3D NoCs — Unifying inter & intra chip communication
2010 Loi I. ; Marchal P. ; Pullini A. ; Benini L.
A new physical routing approach for robust bundled signaling on NoC links
2010 M. R. Kakoee; I. Loi; L. Benini
An efficient distributed memory interface for many-core platform with 3D stacked DRAM
2010 Loi I. ; Benini L.
Design space exploration for 3D-stacked DRAMs
2011 Weis C. ; Wehn N. ; Loi I. ; Benini L.
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters
2011 Rahimi A. ; Loi I. ; Kakoee M.R. ; Benini L.
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
2011 Van der Plas G.; Limaye P.; Loi I.; Mercha A.; Oprins H.; Torregiani C.; Thijs S.; Linten D.; Stucchi M.; Katti G.; Velenis D.; Cherman V.; Vandevelde B.; Simons V.; De Wolf I.; Labie R.; Perry D.; Bronckers S.; Minas N.; Cupac M.; Ruythooren W.; Van Olmen J.; Phommahaxay A.; de Potter de ten Broeck M.; Opdebeeck A.; Rakowski M.; De Wachter B.; Dehan M.; Nelis M.; Agarwal R.; Pullini A.; Angiolini F.; Benini L.; Dehaene W.; Travaly Y.; Beyne E.; Marchal P.
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
2011 Loi I.; Angiolini F.; Fujita S.; Mitra S.; Benini L.
Power/performance exploration of single-core and multi-core processor approaches for biomedical signal processing
2011 A. Dogan; D. Atienza; A. Burg; I. Loi; L. Benini
A resilient architecture for low latency communication in shared-L1 processor clusters
2012 Kakoee M.R.; Loi I. ; Benini L.
3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory
2012 G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini
An energy efficient DRAM subsystem for 3D integrated SoCs
2012 Weis C.; Loi I. ; Benini L. ; Wehn N.
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters
2012 Mohammad Reza Kakoee; Igor Loi; Luca Benini
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)
2013 Erfan Azarkhish;Igor Loi;Luca Benini
Configurable Low-Latency Interconnect for Multi-core ClustersVLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
2013 Giulia Beanato;Igor Loi;Giovanni De Micheli;Yusuf Leblebici;Luca Benini
Exploration and Optimization of 3-D Integrated DRAM Subsystems
2013 Christian Weis;Igor Loi;Luca Benini;Norbert Wehn
Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File |
---|---|---|---|---|---|---|
Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow | I. Loi; F. Angiolini; L. Benini | 2007-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
Area and Power Modeling for Networks-on-Chip with Layout Awareness | P. Meloni; I. Loi; F. Angiolini; S. Carta; M. Barbaro; L. Raffo; L. Benini | 2007-01-01 | VLSI DESIGN | - | 1.01 Articolo in rivista | - |
Developing Mesochronous Synchronizers to Enable 3D NoCs | I. Loi; F. Angiolini; L. Benini | 2008-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. | Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L. | 2008-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
Synthesis of low-overhead configurable source routing tables for network interfaces | Loi I.; Angiolini F.; Benini L. | 2009-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
3D NoCs — Unifying inter & intra chip communication | Loi I. ; Marchal P. ; Pullini A. ; Benini L. | 2010-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
A new physical routing approach for robust bundled signaling on NoC links | M. R. Kakoee; I. Loi; L. Benini | 2010-01-01 | - | ACM | 4.01 Contributo in Atti di convegno | - |
An efficient distributed memory interface for many-core platform with 3D stacked DRAM | Loi I. ; Benini L. | 2010-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
Design space exploration for 3D-stacked DRAMs | Weis C. ; Wehn N. ; Loi I. ; Benini L. | 2011-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters | Rahimi A. ; Loi I. ; Kakoee M.R. ; Benini L. | 2011-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology | Van der Plas G.; Limaye P.; Loi I.; Mercha A.; Oprins H.; Torregiani C.; Thijs S.; Linten D.; Stu...cchi M.; Katti G.; Velenis D.; Cherman V.; Vandevelde B.; Simons V.; De Wolf I.; Labie R.; Perry D.; Bronckers S.; Minas N.; Cupac M.; Ruythooren W.; Van Olmen J.; Phommahaxay A.; de Potter de ten Broeck M.; Opdebeeck A.; Rakowski M.; De Wachter B.; Dehan M.; Nelis M.; Agarwal R.; Pullini A.; Angiolini F.; Benini L.; Dehaene W.; Travaly Y.; Beyne E.; Marchal P. | 2011-01-01 | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - | 1.01 Articolo in rivista | - |
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip | Loi I.; Angiolini F.; Fujita S.; Mitra S.; Benini L. | 2011-01-01 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - | 1.01 Articolo in rivista | - |
Power/performance exploration of single-core and multi-core processor approaches for biomedical signal processing | A. Dogan; D. Atienza; A. Burg; I. Loi; L. Benini | 2011-01-01 | - | Springer-Verlag | 4.01 Contributo in Atti di convegno | - |
A resilient architecture for low latency communication in shared-L1 processor clusters | Kakoee M.R.; Loi I. ; Benini L. | 2012-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory | G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini | 2012-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
An energy efficient DRAM subsystem for 3D integrated SoCs | Weis C.; Loi I. ; Benini L. ; Wehn N. | 2012-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters | Mohammad Reza Kakoee; Igor Loi; Luca Benini | 2012-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS | - | 1.01 Articolo in rivista | - |
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) | Erfan Azarkhish;Igor Loi;Luca Benini | 2013-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
Configurable Low-Latency Interconnect for Multi-core ClustersVLSI-SoC: From Algorithms to Circuits and System-on-Chip Design | Giulia Beanato;Igor Loi;Giovanni De Micheli;Yusuf Leblebici;Luca Benini | 2013-01-01 | - | Springer | 2.01 Capitolo / saggio in libro | - |
Exploration and Optimization of 3-D Integrated DRAM Subsystems | Christian Weis;Igor Loi;Luca Benini;Norbert Wehn | 2013-01-01 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - | 1.01 Articolo in rivista | - |
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