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Mostrati risultati da 1 a 20 di 55
Titolo Autore(i) Anno Periodico Editore Tipo File
Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow I. Loi; F. Angiolini; L. Benini 2007-01-01 - s.n 4.01 Contributo in Atti di convegno -
Area and Power Modeling for Networks-on-Chip with Layout Awareness P. Meloni; I. Loi; F. Angiolini; S. Carta; M. Barbaro; L. Raffo; L. Benini 2007-01-01 VLSI DESIGN - 1.01 Articolo in rivista -
Developing Mesochronous Synchronizers to Enable 3D NoCs I. Loi; F. Angiolini; L. Benini 2008-01-01 - s.n 4.01 Contributo in Atti di convegno -
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L. 2008-01-01 - IEEE 4.01 Contributo in Atti di convegno -
Synthesis of low-overhead configurable source routing tables for network interfaces Loi I.; Angiolini F.; Benini L. 2009-01-01 - IEEE Press 4.01 Contributo in Atti di convegno -
A new physical routing approach for robust bundled signaling on NoC links M. R. Kakoee; I. Loi; L. Benini 2010-01-01 - ACM 4.01 Contributo in Atti di convegno -
An efficient distributed memory interface for many-core platform with 3D stacked DRAM Loi I. ; Benini L. 2010-01-01 - IEEE Press 4.01 Contributo in Atti di convegno -
3D NoCs — Unifying inter & intra chip communication Loi I. ; Marchal P. ; Pullini A. ; Benini L. 2010-01-01 - IEEE Press 4.01 Contributo in Atti di convegno -
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters Rahimi A. ; Loi I. ; Kakoee M.R. ; Benini L. 2011-01-01 - IEEE Press 4.01 Contributo in Atti di convegno -
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip Loi I.; Angiolini F.; Fujita S.; Mitra S.; Benini L. 2011-01-01 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS - 1.01 Articolo in rivista -
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology Van der Plas G.; Limaye P.; Loi I.; Mercha A.; Oprins H.; Torregiani C.; Thijs S.; Linten D.; Stu...cchi M.; Katti G.; Velenis D.; Cherman V.; Vandevelde B.; Simons V.; De Wolf I.; Labie R.; Perry D.; Bronckers S.; Minas N.; Cupac M.; Ruythooren W.; Van Olmen J.; Phommahaxay A.; de Potter de ten Broeck M.; Opdebeeck A.; Rakowski M.; De Wachter B.; Dehan M.; Nelis M.; Agarwal R.; Pullini A.; Angiolini F.; Benini L.; Dehaene W.; Travaly Y.; Beyne E.; Marchal P. 2011-01-01 IEEE JOURNAL OF SOLID-STATE CIRCUITS - 1.01 Articolo in rivista -
Design space exploration for 3D-stacked DRAMs Weis C. ; Wehn N. ; Loi I. ; Benini L. 2011-01-01 - IEEE Press 4.01 Contributo in Atti di convegno -
Power/performance exploration of single-core and multi-core processor approaches for biomedical signal processing A. Dogan; D. Atienza; A. Burg; I. Loi; L. Benini 2011-01-01 - Springer-Verlag 4.01 Contributo in Atti di convegno -
An energy efficient DRAM subsystem for 3D integrated SoCs Weis C.; Loi I. ; Benini L. ; Wehn N. 2012-01-01 - IEEE Press 4.01 Contributo in Atti di convegno -
A resilient architecture for low latency communication in shared-L1 processor clusters Kakoee M.R.; Loi I. ; Benini L. 2012-01-01 - IEEE Press 4.01 Contributo in Atti di convegno -
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters Mohammad Reza Kakoee; Igor Loi; Luca Benini 2012-01-01 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS - 1.01 Articolo in rivista -
3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini 2012-01-01 - IEEE Press 4.01 Contributo in Atti di convegno -
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects Erfan Azarkhish;Luca Benini;Igor Loi 2013-01-01 IET COMPUTERS & DIGITAL TECHNIQUES - 1.01 Articolo in rivista -
Exploration and Optimization of 3-D Integrated DRAM Subsystems Christian Weis;Igor Loi;Luca Benini;Norbert Wehn 2013-01-01 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS - 1.01 Articolo in rivista -
A high-performance multiported L2 memory IP for scalable three-dimensional integration2013 IEEE International 3D Systems Integration Conference (3DIC) Erfan Azarkhish;Igor Loi;Luca Benini 2013-01-01 - 2013 IEEE Conference Proceedings 4.01 Contributo in Atti di convegno -
Mostrati risultati da 1 a 20 di 55
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