Networks-on-chip have been developed in the last few years to address the scalability challenges of global on-chip communication. VLSI technology is now rapidly moving into vertical stacking to overcome fundamental communication and integration bottlenecks, however this technology is not mature yet, and significant reliability challenges must be overcome. In this paper we describe our effort in establishing a 3DNoC design flow and in designing circuits and architectural solutions for variability and reliability characterization and tolerance.

Loi I. , Marchal P. , Pullini A. , Benini L. (2010). 3D NoCs — Unifying inter & intra chip communication. s.l : IEEE Press.

3D NoCs — Unifying inter & intra chip communication

LOI, IGOR;BENINI, LUCA
2010

Abstract

Networks-on-chip have been developed in the last few years to address the scalability challenges of global on-chip communication. VLSI technology is now rapidly moving into vertical stacking to overcome fundamental communication and integration bottlenecks, however this technology is not mature yet, and significant reliability challenges must be overcome. In this paper we describe our effort in establishing a 3DNoC design flow and in designing circuits and architectural solutions for variability and reliability characterization and tolerance.
2010
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
3337
3340
Loi I. , Marchal P. , Pullini A. , Benini L. (2010). 3D NoCs — Unifying inter & intra chip communication. s.l : IEEE Press.
Loi I. ; Marchal P. ; Pullini A. ; Benini L.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/95322
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