Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area- and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of three-dimensional die stacks with a large number of TSVs. This paper presents a defect-tolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy. This technique is ideally suited for three-dimensional network-on-chip (NoC) links. Simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a NoC switch, which leads a modest 2.1% increase the total switch area) in 130nm technology, with minimal impact of VLSI design and test flows.

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links / Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L.. - STAMPA. - (2008), pp. 598-602. (Intervento presentato al convegno ICCAD 2008. IEEE/ACM International Conference on Computer-Aided Design. tenutosi a San Jose, California nel 10-13/11/2008).

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.

LOI, IGOR;BENINI, LUCA
2008

Abstract

Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area- and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of three-dimensional die stacks with a large number of TSVs. This paper presents a defect-tolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy. This technique is ideally suited for three-dimensional network-on-chip (NoC) links. Simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a NoC switch, which leads a modest 2.1% increase the total switch area) in 130nm technology, with minimal impact of VLSI design and test flows.
2008
Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on Computer-Aided Design
598
602
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links / Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L.. - STAMPA. - (2008), pp. 598-602. (Intervento presentato al convegno ICCAD 2008. IEEE/ACM International Conference on Computer-Aided Design. tenutosi a San Jose, California nel 10-13/11/2008).
Loi I.; Mitra S.; Lee T.H.; Fujita S.; Benini L.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/69827
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