In this paper we present a simulation study of a novel Double-Gate (DG) Ferroelectric FET (Fe-FET) architecture, exhibiting a subthreshold swing well below 60 m V/dee with a hysteresis-free behavior. The new device topology is based on the interposition of a floating gate between the ferroelectric layer and the gate oxide. The ferroelectric layer can be extended above the source and drain regions, so that its capacitance can be suitably optimized to ensure device stability. Under the assumption of a fixed mobility, the on-state current improvement over a standard DG MOSFET turns out to be 86%, with a degradation of the intrinsic delay time of about 12%.
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