μDMA: An autonomous I/O subsystem for IoT end-nodes

The Internet of Things revolution requires long-battery-lifetime, autonomous end-nodes capable of probing the environment from multiple sensors and transmit it wirelessly after data-fusion, recognition, and classification. Duty-cycling is a well-known approach to extend battery lifetime: it allows to keep the hardware resources of the micro-controller implementing the end-node (MCUs) in sleep mode for most of the time, and activate them on-demand only during data acquisition or processing phases. To this end, most advanced MCUs feature autonomous I/O subsystems able to acquire data from multiple sensors when the CPU is in idle state. However, in these traditional I/O subsystems the interconnect is shared with the processing resources of the system, both converging in a single-port system memory. Moreover, both I/O and the data processing subsystems stand in some power domain. In this work we overcome the bandwidth and power-management limitations of current MCU’s I/O architectures introducing an autonomous I/O subsystem coupling an I/O DMA tightly-coupled with a multi-banked system memory controlled by a tiny CPU, which stands on a dedicated power domain. The proposed architecture achieves a transfer efficiency of 84% when considering only data transfers, and 53% if we consider also the overhead of the runtime running on the controlling processor, reducing the operating frequency of the I/O subsystem by up to 2.2x with respect to traditional MCU architectures.