Today Tunnel FETs are perceived as the most promising small slope transistors, that may enable a significant decrease in the power supply of integrated circuits and thus an improvement of their energy efficiency. However, many experimental results largely differ from the simulations of ideal Tunnel FETs, in fact simulations report small sub-threshold swing (SS) values over several orders of magnitudes of drain current, low off-current, and high on-current values, which, unfortunately, are not observed in experimental results. Such a discrepancy between simulated and experimental IV characteristics suggest that the modeling of idealized TFETs may be neglecting non-ideal effects that play an important role in measured devices. In this respect, several experimental papers made an explicit statement about the fact that the SS values observed in measured transistors are severely degraded by trap-assisted-tunneling (TAT) via interface or bulk traps. This problem may be particularly challenging in III-V based Tunnel FETS which, while they promise large tunneling currents thanks to the relatively small band-gap, may suffer of larger trap densities compared to Si or SiGe transistors.

Esseni, D., Pala, M., Gnani, E., Sangiorgi, E. (2015). Influence of interface traps on the performance of Tunnel FETs. Institute of Electrical and Electronics Engineers Inc. [10.1109/E3S.2015.7336798].

Influence of interface traps on the performance of Tunnel FETs

ESSENI, DAVID;GNANI, ELENA;SANGIORGI, ENRICO
2015

Abstract

Today Tunnel FETs are perceived as the most promising small slope transistors, that may enable a significant decrease in the power supply of integrated circuits and thus an improvement of their energy efficiency. However, many experimental results largely differ from the simulations of ideal Tunnel FETs, in fact simulations report small sub-threshold swing (SS) values over several orders of magnitudes of drain current, low off-current, and high on-current values, which, unfortunately, are not observed in experimental results. Such a discrepancy between simulated and experimental IV characteristics suggest that the modeling of idealized TFETs may be neglecting non-ideal effects that play an important role in measured devices. In this respect, several experimental papers made an explicit statement about the fact that the SS values observed in measured transistors are severely degraded by trap-assisted-tunneling (TAT) via interface or bulk traps. This problem may be particularly challenging in III-V based Tunnel FETS which, while they promise large tunneling currents thanks to the relatively small band-gap, may suffer of larger trap densities compared to Si or SiGe transistors.
2015
2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings
1
1
Esseni, D., Pala, M., Gnani, E., Sangiorgi, E. (2015). Influence of interface traps on the performance of Tunnel FETs. Institute of Electrical and Electronics Engineers Inc. [10.1109/E3S.2015.7336798].
Esseni, D.; Pala, M.; Gnani, E.; Sangiorgi, E.
File in questo prodotto:
Eventuali allegati, non sono esposti

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/555338
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? ND
social impact