In this paper, we present an analysis of the degradation and recovery mechanisms in p-channel power U-MOSFETs due to Negative Bias Temperature Instability (NBTI). In particular, we study the influence of NBTI on threshold voltage and sub-threshold slope, which are the main figures of merit affected by charge trapping in the oxide and by interface state generation. The temperature and bias dependence of NBTI phenomena have been investigated. As a result, we report a higher degradation with the temperature and gate bias increase. On the other hand, by monitoring the recovery phase in different conditions, we found out similar behaviors heavily reported in CMOS technology, which are: i) recovery mechanism is mainly due to oxide detrapping charge; ii) higher temperatures allow a faster and larger recovery, hence it is an accelerator factor also for this mechanism; iii) the oxide defects, involved in the detrapping phase, have an energy position confined in the band-gap of the silicon.
Andrea Natale Tallarico, Paolo Magnone, Giacomo Barletta, Angelo Magrì, Enrico Sangiorgi, Claudio Fiegna (2015). Influence of bias and temperature conditions on NBTI physical mechanisms in p-channel power U-MOSFETs. SOLID-STATE ELECTRONICS, 108, 42-46 [10.1016/j.sse.2014.12.009].
Influence of bias and temperature conditions on NBTI physical mechanisms in p-channel power U-MOSFETs
TALLARICO, ANDREA NATALE;SANGIORGI, ENRICO;FIEGNA, CLAUDIO
2015
Abstract
In this paper, we present an analysis of the degradation and recovery mechanisms in p-channel power U-MOSFETs due to Negative Bias Temperature Instability (NBTI). In particular, we study the influence of NBTI on threshold voltage and sub-threshold slope, which are the main figures of merit affected by charge trapping in the oxide and by interface state generation. The temperature and bias dependence of NBTI phenomena have been investigated. As a result, we report a higher degradation with the temperature and gate bias increase. On the other hand, by monitoring the recovery phase in different conditions, we found out similar behaviors heavily reported in CMOS technology, which are: i) recovery mechanism is mainly due to oxide detrapping charge; ii) higher temperatures allow a faster and larger recovery, hence it is an accelerator factor also for this mechanism; iii) the oxide defects, involved in the detrapping phase, have an energy position confined in the band-gap of the silicon.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.