We apply state-of-the-art simulation to investigate the possibility to scale the UTB-DG MOSFET using rather conventional SiO2-based dielectrics with a minimum thickness of 1 nm, a lower limit set by the need for process yield and reproducibility. The analysis include short-channel effects, gate leakage tunneling current, ON-current and the intrinsic switching delay-time CV/I.
N. Barin , M. Braccioli , C. Fiegna , E. Sangiorgi (2005). Scaling the High-Performance Double-Gate SOI MOSFET down to the 32 nm Technology Node with SiO2-based Gate Stacks. PISCATAWAY, NJ : IEEE.
Scaling the High-Performance Double-Gate SOI MOSFET down to the 32 nm Technology Node with SiO2-based Gate Stacks
BRACCIOLI, MARCO;FIEGNA, CLAUDIO;SANGIORGI, ENRICO
2005
Abstract
We apply state-of-the-art simulation to investigate the possibility to scale the UTB-DG MOSFET using rather conventional SiO2-based dielectrics with a minimum thickness of 1 nm, a lower limit set by the need for process yield and reproducibility. The analysis include short-channel effects, gate leakage tunneling current, ON-current and the intrinsic switching delay-time CV/I.File in questo prodotto:
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