AZARKHISH, ERFAN
AZARKHISH, ERFAN
DIPARTIMENTO DI INGEGNERIA DELL'ENERGIA ELETTRICA E DELL'INFORMAZIONE "GUGLIELMO MARCONI"
A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge
2021 Jokic P.; Azarkhish E.; Cattenoz R.; Turetken E.; Benini L.; Emery S.
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes
2018 Azarkhish, Erfan*; Rossi, Davide; Loi, Igor; Benini, Luca
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters
2017 Payami, Maryam*; Azarkhish, Erfan; Loi, Igor; Benini, Luca
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube
2017 Azarkhish, Erfan; Pfister, Christoph; Rossi, Davide; Loi, Igor; Benini, Luca
Design and evaluation of a processing-in-memory architecture for the smart memory cube
2016 Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca
A Modular Shared L2 Memory Design for 3-D Integration
2015 Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca
High Performance AXI-4.0 Based Interconnect for Extensible Smart Memory Cubes
2015 Azarkhish, Erfan; Rossi, Davide; Loi, Igor; Benini, Luca
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)
2013 Erfan Azarkhish;Igor Loi;Luca Benini
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects
2013 Erfan Azarkhish;Luca Benini;Igor Loi
A high-performance multiported L2 memory IP for scalable three-dimensional integration2013 IEEE International 3D Systems Integration Conference (3DIC)
2013 Erfan Azarkhish;Igor Loi;Luca Benini