BENINI, LUCA
BENINI, LUCA
DIPARTIMENTO DI INGEGNERIA DELL'ENERGIA ELETTRICA E DELL'INFORMAZIONE "GUGLIELMO MARCONI"
Docenti di ruolo di Ia fascia
BENINI L; L. BENINI; Luca Benini
0, 1, 2, many - A classroom occupancy monitoring system for smart public buildings
2014 Paci, Francesco; Brunelli, Davide; Benini, Luca
16 Gb/s Microring-to-Microring Photonic Link in 45 nm Monolithic Zero-Change CMOS
2018 Marco Eppenberger; Arne Josten; Juerg Leuthold; Benedikt Bäuerle; Luca Alloatti; Luca Benini; David Moor
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
2016 Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Adam; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca
3D CV descriptor on parallel heterogeneous platforms
2015 Palossi, Daniele; Ruggiero, Martino; Benini, Luca
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)
2013 Erfan Azarkhish;Igor Loi;Luca Benini
3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks
2011 C. Seiculescu; S. Murali; L. Benini; G. De Micheli
3D NoCs — Unifying inter & intra chip communication
2010 Loi I. ; Marchal P. ; Pullini A. ; Benini L.
3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory
2012 G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini
3dID: a low-power, low-cost hand motion capture device
2006 M. Sama; V. Pacella; E. Farella; L. Benini; B. Riccó
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode
2021 Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi I.; Chen J.; Flamand E.; Benini L.
4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster
2016 Gautschi, Michael; Schaffner, Michael; Gurkaynak, Frank K.; Benini, Luca
64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique
2022 Harel, O; Casarrubias, EN; Eggimann, M; Gurkaynak, F; Benini, L; Teman, A; Giterman, R; Burg, A
A 'New Ara' for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
2022 Perotti M.; Cavalcante M.; Wistoff N.; Andri R.; Cavigelli L.; Benini L.
A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
2015 Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse, Philippe; Benini, Luca
A 0.45-0.7 v 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation
2018 Choi, Woo-Seok*; Shu, Guanghua; Talegaonkar, Mrunmay; Liu, Yubo; Wei, Da; Benini, Luca; Hanumolu, Pavan Kumar
A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS
2015 Choi, Woo-Seok; Shu, Guanghua; Talegaonkar, Mrunmay; Liu, Yubo; Wei, Da; Benini, Luca; Hanumolu, Pavan Kumar
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL
2021 Elnaqib A.; Okuhara H.; Jang T.; Rossi D.; Benini L.
A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI
2019 Mach S.; Schuiki F.; Zaruba F.; Benini L.
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
2021 Garofalo A.; Ottavi G.; Di Mauro A.; Conti F.; Tagliavini G.; Benini L.; Rossi D.
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range
2021 Benz T.; Bertaccini L.; Zaruba F.; Schuiki F.; Gurkaynak F.K.; Benini L.
| Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File |
|---|---|---|---|---|---|---|
| 0, 1, 2, many - A classroom occupancy monitoring system for smart public buildings | Paci, Francesco; Brunelli, Davide; Benini, Luca | 2014-01-01 | - | - | 4.01 Contributo in Atti di convegno | - |
| 16 Gb/s Microring-to-Microring Photonic Link in 45 nm Monolithic Zero-Change CMOS | Marco Eppenberger; Arne Josten; Juerg Leuthold; Benedikt Bäuerle; Luca Alloatti; Luca Benini; Dav...id Moor | 2018-01-01 | - | - | 4.01 Contributo in Atti di convegno | - |
| 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing | Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gurkaynak, Frank Kagan; Teman, Ada...m; Constantin, Jeremy; Burg, Andreas; Miro-Panades, Ivan; Beign, Edith; Clermidy, Fabien; Abouzeid, Fady; Flatresse, Philippe; Benini, Luca | 2016-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| 3D CV descriptor on parallel heterogeneous platforms | Palossi, Daniele; Ruggiero, Martino; Benini, Luca | 2015-01-01 | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | - | 1.01 Articolo in rivista | - |
| 3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) | Erfan Azarkhish;Igor Loi;Luca Benini | 2013-01-01 | - | IEEE | 4.01 Contributo in Atti di convegno | - |
| 3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks | C. Seiculescu; S. Murali; L. Benini; G. De Micheli | 2011-01-01 | - | Springer | 2.01 Capitolo / saggio in libro | - |
| 3D NoCs — Unifying inter & intra chip communication | Loi I. ; Marchal P. ; Pullini A. ; Benini L. | 2010-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
| 3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory | G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini | 2012-01-01 | - | IEEE Press | 4.01 Contributo in Atti di convegno | - |
| 3dID: a low-power, low-cost hand motion capture device | M. Sama; V. Pacella; E. Farella; L. Benini; B. Riccó | 2006-01-01 | - | European Design and Automation Association | 4.01 Contributo in Atti di convegno | - |
| 4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode | Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi... I.; Chen J.; Flamand E.; Benini L. | 2021-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | 09365939.pdf; paper_proofread_d.pdf |
| 4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster | Gautschi, Michael; Schaffner, Michael; Gurkaynak, Frank K.; Benini, Luca | 2016-01-01 | DIGEST OF TECHNICAL PAPERS - IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| 64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique | Harel, O; Casarrubias, EN; Eggimann, M; Gurkaynak, F; Benini, L; Teman, A; Giterman, R; Burg, A | 2022-01-01 | IEEE SOLID-STATE CIRCUITS LETTERS | - | 1.01 Articolo in rivista | - |
| A 'New Ara' for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design | Perotti M.; Cavalcante M.; Wistoff N.; Andri R.; Cavigelli L.; Benini L. | 2022-01-01 | - | - | 4.01 Contributo in Atti di convegno | - |
| A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology | Rossi, Davide; Pullini, Antonio; Gautschi, Michael; Loi, Igor; Gurkaynak, Frank Kagan; Flatresse,... Philippe; Benini, Luca | 2015-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | A −1.8V to 0.9V body bias, 60 GOPS-W 4-core cluster in low-power 28nm UTBB FD-SOI technology.pdf; A -1.8V to 0.9V Body Bias_Postprint..pdf |
| A 0.45-0.7 v 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation | Choi, Woo-Seok*; Shu, Guanghua; Talegaonkar, Mrunmay; Liu, Yubo; Wei, Da; Benini, Luca; Hanumolu,... Pavan Kumar | 2018-01-01 | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - | 1.01 Articolo in rivista | - |
| A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS | Choi, Woo-Seok; Shu, Guanghua; Talegaonkar, Mrunmay; Liu, Yubo; Wei, Da; Benini, Luca; Hanumolu, ...Pavan Kumar | 2015-01-01 | DIGEST OF TECHNICAL PAPERS - IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |
| A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL | Elnaqib A.; Okuhara H.; Jang T.; Rossi D.; Benini L. | 2021-01-01 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS | - | 1.01 Articolo in rivista | A 0.5GHz 0.35mW.pdf; A 0.5GHz 0.35mW_Pprint.pdf |
| A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI | Mach S.; Schuiki F.; Zaruba F.; Benini L. | 2019-01-01 | - | IEEE Computer Society | 4.01 Contributo in Atti di convegno | A 0.80 pJ-flop, 1.24 Tflop-sW 8-to-64 bit_preprint.pdf |
| A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode | Garofalo A.; Ottavi G.; Di Mauro A.; Conti F.; Tagliavini G.; Benini L.; Rossi D. | 2021-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | DUSTIN_REDUX.pdf |
| A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range | Benz T.; Bertaccini L.; Zaruba F.; Schuiki F.; Gurkaynak F.K.; Benini L. | 2021-01-01 | - | Institute of Electrical and Electronics Engineers Inc. | 4.01 Contributo in Atti di convegno | - |