In this paper, we present a novel testbed based on a DC-DC synchronous Buck power converter, allowing the reliability analysis of GaN HEMTs with p-type gate. In particular, it is possible to monitor the drift of the device parameters to highlight the main degradation mechanisms affecting GaN transistors in power electronic applications. Stress is applied when HEMTs work within a practical 48/12V DC-DC converter operating at 1 MHz switching frequency and 4A output current. The reported analysis has been carried out under two different conditions, namely soft and hard stress, inducing a relatively low and high junction temperature, respectively. Results show that the high-side transistor of a DC-DC Buck converter is more prone to degradation, due to a larger threshold voltage and on-resistance drift. Moreover, based on the results of a validation analysis of the proposed characterization approach, the gate stack appears as the weaker transistor region causing device failure in the case of hard stress. Finally, a completely recoverable and a permanent VTH and RON drift is observed in the case of soft and hard stress, respectively.
Capasso G., Zanuccoli M., Tallarico A.N., Fiegna C. (2022). A novel approach to analyze the reliability of GaN power HEMTs operating in a DC-DC Buck converter. Editions Frontieres [10.1109/ESSDERC55479.2022.9947200].
A novel approach to analyze the reliability of GaN power HEMTs operating in a DC-DC Buck converter
Capasso G.
;Zanuccoli M.;Tallarico A. N.;Fiegna C.
2022
Abstract
In this paper, we present a novel testbed based on a DC-DC synchronous Buck power converter, allowing the reliability analysis of GaN HEMTs with p-type gate. In particular, it is possible to monitor the drift of the device parameters to highlight the main degradation mechanisms affecting GaN transistors in power electronic applications. Stress is applied when HEMTs work within a practical 48/12V DC-DC converter operating at 1 MHz switching frequency and 4A output current. The reported analysis has been carried out under two different conditions, namely soft and hard stress, inducing a relatively low and high junction temperature, respectively. Results show that the high-side transistor of a DC-DC Buck converter is more prone to degradation, due to a larger threshold voltage and on-resistance drift. Moreover, based on the results of a validation analysis of the proposed characterization approach, the gate stack appears as the weaker transistor region causing device failure in the case of hard stress. Finally, a completely recoverable and a permanent VTH and RON drift is observed in the case of soft and hard stress, respectively.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
