In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 -4im. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: 1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; 2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and 3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort. ) ©1999 IEEE.
Baccarani G., Reggiani S. (1999). A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects. IEEE TRANSACTIONS ON ELECTRON DEVICES, 46(8), 1656-1666 [10.1109/16.777154].
A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects
Baccarani G.;Reggiani S.
1999
Abstract
In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 -4im. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: 1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; 2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and 3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort. ) ©1999 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.