Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias

A new concept of noise reduction in CMOS circuits is presented taking advantage of a strong reduction of MOSFET under switched gate and forward substrate bias. The effect of forward substrate bias on substrate bias is most effective when applied during the off-state of the transistor. A bias scheme adopting forward substrate bias only during the transistor off-state is suggested by the measurement results of transconductance efficiency gm Id and intrinsic voltage gain gm gds showing that these figures of merit are degraded when a forward substrate bias is applied during the on-state. As a first example exploiting the found noise reduction on circuit level, a 14 GHz pMOS VCO is presented. Our results show a significant reduction of close to carrier phase noise when a forward substrate bias is applied to the MOSFETs providing the negative conductance stage for the oscillation of the VCO. The outlined principles can be extended to other circuits and motivate new topologies and biasing schemes for analog and radio frequency CMOS circuits.