BTI saturation and universal relaxation in SiC power MOSFETs

This work focuses on the positive bias temperature instability of SiC-based MOSFETs under different stress voltages and temperatures. Stress experiments demonstrate that the threshold voltage shift (∆Vth) does not follow a conventional power law for long stress time, but exhibits a saturating log- time dependence attributed to the charge trapping in the pre-existing defects at the SiC/SiO2 interface or in the SiO2 layer. The maximum Vth shift (∆Vmax), which is a function of the total trap density, increases with the stress voltage (Vstress) and decreases for temperatures higher than 50 °C. The time constant of the traps (τ0) also shows an uptrend with Vstress with a maximum value of around 50 °C. Moreover, the trap energy distribution (γ) slightly increases with temperature. The recovery analysis shows that an empiric universal relaxation function well describes the data with a dispersion parameter (β) that follows the Arrhenius law. Finally, the Vth recovery, after the same Vstress, is enhanced with temperature and also depicts a linear behavior on the Arrhenius plot. This indicates that the charge de-trapping process is thermally activated and explains the low degradation observed at high temperatures during the stress phase.