This paper presents an Analog Front-End for integrated Wake-Up Radios. The proposed Analog Front-End is composed of an envelope detector, a Schmitt trigger and a biasing block and has three distinctive features: i) clockless solution, which does not require an always-on oscillator; ii) an envelope detector with band-pass response which leads to smaller capacitance, thus easier integration, and low-frequency noise suppression; iii) temperature compensated biasing scheme. An active scheme for the detector is used based on MOSFETs operated in the subthreshold region with a self-biased topology. Advantages and drawbacks of the proposed architecture are analyzed. A prototype was fabricated in the STMicroelectronics 90-nm BCD technology. The overall power consumption, excluding the biasing block, is 36 nW at 1.2 V. A 10 -3 Bit Error Rate is measured with a 771-MHz, 2-kbit/s OOK modulated input signal with -46 dBm power at room temperature and at -20 °C, and with almost -43 dBm power at 60 °C.
Elgani A.M., Renzini F., Perilli L., Franchi Scarselli E., Gnudi A., Canegallo R., et al. (2020). A Clockless Temperature-Compensated Nanowatt Analog Front-End for Wake-Up Radios Based on a Band-Pass Envelope Detector. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, 67(8), 2612-2624 [10.1109/TCSI.2020.2987850].
A Clockless Temperature-Compensated Nanowatt Analog Front-End for Wake-Up Radios Based on a Band-Pass Envelope Detector
Elgani A. M.
;Renzini F.;Perilli L.;Franchi Scarselli E.;Gnudi A.;
2020
Abstract
This paper presents an Analog Front-End for integrated Wake-Up Radios. The proposed Analog Front-End is composed of an envelope detector, a Schmitt trigger and a biasing block and has three distinctive features: i) clockless solution, which does not require an always-on oscillator; ii) an envelope detector with band-pass response which leads to smaller capacitance, thus easier integration, and low-frequency noise suppression; iii) temperature compensated biasing scheme. An active scheme for the detector is used based on MOSFETs operated in the subthreshold region with a self-biased topology. Advantages and drawbacks of the proposed architecture are analyzed. A prototype was fabricated in the STMicroelectronics 90-nm BCD technology. The overall power consumption, excluding the biasing block, is 36 nW at 1.2 V. A 10 -3 Bit Error Rate is measured with a 771-MHz, 2-kbit/s OOK modulated input signal with -46 dBm power at room temperature and at -20 °C, and with almost -43 dBm power at 60 °C.File | Dimensione | Formato | |
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