Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for low-power applications; several methods of phase generation have been proposed, one of which is phase interpolation. We propose a phase interpolator (PI) that employs the concept of constant-slope operation. Consequently, a low-power highly-linear operation is coupled with the wide dynamic range (i.e., phase wrapping) capabilities of a PI. Furthermore, the PI is powered by a low-dropout regulator (LDO) supporting fast transient operation. Implemented in 65-nm CMOS technology, it consumes 350μ W at a 1.2-V supply and a 0.5-GHz clock; it achieves energy efficiency 4× -15× lower than state-of-the-art (SoA) digital-to-time converters (DTCs) and an integral non-linearity (INL) of 2.5× -3.1× better than SoA PIs, striking a good balance between linearity and energy efficiency.

A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL

Okuhara H.;Rossi D.;Benini L.
2021

Abstract

Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for low-power applications; several methods of phase generation have been proposed, one of which is phase interpolation. We propose a phase interpolator (PI) that employs the concept of constant-slope operation. Consequently, a low-power highly-linear operation is coupled with the wide dynamic range (i.e., phase wrapping) capabilities of a PI. Furthermore, the PI is powered by a low-dropout regulator (LDO) supporting fast transient operation. Implemented in 65-nm CMOS technology, it consumes 350μ W at a 1.2-V supply and a 0.5-GHz clock; it achieves energy efficiency 4× -15× lower than state-of-the-art (SoA) digital-to-time converters (DTCs) and an integral non-linearity (INL) of 2.5× -3.1× better than SoA PIs, striking a good balance between linearity and energy efficiency.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS
Elnaqib A.; Okuhara H.; Jang T.; Rossi D.; Benini L.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/791999
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