We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph mode is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.
X. Ma, J. Huang, F. Chiminazzo, D. Rossi, C. Metra, F. Lombardi (2008). Resistive Crossbar Switching Networks to Implement Inherently Fault Tolerant Nano LUTs. LOS ALAMITOS : C. Metra, A. DeHon.
Resistive Crossbar Switching Networks to Implement Inherently Fault Tolerant Nano LUTs
ROSSI, DANIELE;METRA, CECILIA;
2008
Abstract
We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph mode is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
