Size Dependence of Surface-Roughness Limited Mobility in Silicon Nanowire FETs

Lateral size effects on surface-roughness limited mobility in silicon nanowire FETs are analyzed by means of a full-quantum 3-D self-consistent simulation. A statistical analysis is carried out by considering different realizations of the potential roughness at the Si-SiO_2 interfaces. Nanowires with lateral sections varying from 3x3 to 7x7 nm^2 are considered. Effective mobility is computed by evaluating the electron density in a reducd channel region to eliminate parasitic effects from the contacts. It si found that transport in wires with the smallest section is dominated by scattering due to the potential fluctuations, resulting in a larger standard deviation of the effective mobility, whereas it is dominated by transverse-mode coupling in wires with larger section, resulting in a stronger influence of surface roughness at high gate voltages.