Ultra-low power computing is a key enabler of deeply embedded platforms used in domains such as distributed sensing, internet of things, wearable computing. The rising computational demands and high dynamic of target algorithms often call for hardware support of floating-point (FP) arithmetic and high system energy efficiency. In light of transprecision computing, where accuracy of data is consciously changed during the execution of applications, custom FP types are being used to optimize a wide range of problems. We support two such custom types - one 16 bit and one 8 bit wide - together with IEEE binary16 as a set of 'smallFloat' formats. We present an FP arithmetic unit capable of performing basic operations on smallFloat formats as well as conversions. To boost performance and energy efficiency, the smallFloat unit is extended with SIMD-style vectorization support to operate on a conventional word width of 32 bit. Finally, it is added into the execution stage of a low-power 32-bit RISC-V processor core and integrated as part of an SoC in a 65nm process. We show that the energy efficiency for processing smallFloat data in this amended system is 18% higher than the binary32 baseline, thus enabling hardware-supported power savings for applications making use of transprecision.

A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing / Mach, Stefan; Rossi, Davide; Tagliavini, Giuseppe; Marongiu, Andrea; Benini, Luca. - ELETTRONICO. - (2018), pp. 8351816.1-8351816.5. (Intervento presentato al convegno 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 tenutosi a Firenze (Italy) nel 27–30 May 2018) [10.1109/ISCAS.2018.8351816].

A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing

Rossi, Davide;Tagliavini, Giuseppe
;
Marongiu, Andrea;Benini, Luca
2018

Abstract

Ultra-low power computing is a key enabler of deeply embedded platforms used in domains such as distributed sensing, internet of things, wearable computing. The rising computational demands and high dynamic of target algorithms often call for hardware support of floating-point (FP) arithmetic and high system energy efficiency. In light of transprecision computing, where accuracy of data is consciously changed during the execution of applications, custom FP types are being used to optimize a wide range of problems. We support two such custom types - one 16 bit and one 8 bit wide - together with IEEE binary16 as a set of 'smallFloat' formats. We present an FP arithmetic unit capable of performing basic operations on smallFloat formats as well as conversions. To boost performance and energy efficiency, the smallFloat unit is extended with SIMD-style vectorization support to operate on a conventional word width of 32 bit. Finally, it is added into the execution stage of a low-power 32-bit RISC-V processor core and integrated as part of an SoC in a 65nm process. We show that the energy efficiency for processing smallFloat data in this amended system is 18% higher than the binary32 baseline, thus enabling hardware-supported power savings for applications making use of transprecision.
2018
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
1
5
A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing / Mach, Stefan; Rossi, Davide; Tagliavini, Giuseppe; Marongiu, Andrea; Benini, Luca. - ELETTRONICO. - (2018), pp. 8351816.1-8351816.5. (Intervento presentato al convegno 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 tenutosi a Firenze (Italy) nel 27–30 May 2018) [10.1109/ISCAS.2018.8351816].
Mach, Stefan; Rossi, Davide; Tagliavini, Giuseppe; Marongiu, Andrea; Benini, Luca
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/652240
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