Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

This letter presents a high speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which is fabricated using a top down process technology. The NW cell exhibits faster program and erase (P/E) speed compared to the corresponding planar device; 1 us for programming at Vgs = 11V and 1 ms for erasing at Vgs = -11V with a threshold voltage shift of 2.6 V using the Fowler-Nordhein tunneling mechanism. A thes P/E conditions, the planar device does not show any appreciabl change. The improvement is originated from: 1) increased electric field at the Si-SiO_2 interface; 2) reducedeffective tunnel barrier width; 3) low electric field in the blocking oxide, as nalyzed through simulation. In addition, good data retention makes the NW-based SONOS cell a potential candidate for future high speed low voltage NAND-type non-volatile flash memory applications.