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EnglishTechnology scaling enables today the design of sensor-based ultra-low cost chips well suited for emerging applications such as wireless body sensor networks, urban life and environment monitoring. Energy consumption is the key limiting factor of this up-coming revolution and memories are often the energy bottleneck mainly due to leakage power. This paper proposes an ultra-low power multi-core architecture targeting eHealth monitoring systems, where applications involve collection of sequences of slow biomedical signals and highly parallel computations at very low voltage. We propose a hybrid memory architecture that combines 6T-SRAM and 8T-SRAM operating in the same voltage domain and capable of dispatching at high voltage a normal operation and at low voltage a fully reliable small memory partition (8T) while the rest of the memory (6T) is state-retentive. Our architecture offers significant energy savings with a low area overhead in typical eHealth Compressed Sensing-based applications
| Titolo: | Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors |
| Autore/i: | BORTOLOTTI, DANIELE; BARTOLINI, ANDREA; Weis, Christian; ROSSI, DAVIDE; BENINI, LUCA |
| Autore/i Unibo: | |
| Anno: | 2014 |
| Titolo del libro: | Conference Design, Automation and Test in Europe (DATE) |
| Pagina iniziale: | 1 |
| Pagina finale: | 6 |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.7873/DATE.2014.182 |
| Abstract: | Technology scaling enables today the design of sensor-based ultra-low cost chips well suited for emerging applications such as wireless body sensor networks, urban life and environment monitoring. Energy consumption is the key limiting factor of this up-coming revolution and memories are often the energy bottleneck mainly due to leakage power. This paper proposes an ultra-low power multi-core architecture targeting eHealth monitoring systems, where applications involve collection of sequences of slow biomedical signals and highly parallel computations at very low voltage. We propose a hybrid memory architecture that combines 6T-SRAM and 8T-SRAM operating in the same voltage domain and capable of dispatching at high voltage a normal operation and at low voltage a fully reliable small memory partition (8T) while the rest of the memory (6T) is state-retentive. Our architecture offers significant energy savings with a low area overhead in typical eHealth Compressed Sensing-based applications |
| Data stato definitivo: | 17-dic-2015 |
| Appare nelle tipologie: | 4.01 Contributo in Atti di convegno |
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http://hdl.handle.net/11585/525071
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