Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability

This paper proposes a near-zero area overhead adaptive guardbanding technique to combat CMOS variability for errortolerant (probabilistic) applications as well as traditional error-intolerant applications. The proposed technique leverages a combination of accurate design time analysis and a minimally intrusive runtime technique to mitigate Process, Voltage, and Temperature (PVT) variations. We demonstrate our approach on a 32-bit in-order RISC processor with full post Placement and Routing (P&R) layout results in 45nm TSMC technology. The adaptive guardbanding technique eliminates conservative guardbands on frequency due to PVT variations, thus increases the throughput of probabilistic applications up to 1.9× over the traditional worstcase design. For error-intolerant applications, we introduce the notion of Sequence-Level Vulnerability (SLV) that utilizes circuit-level vulnerability for constructing high-level software knowledge as metadata. Using SLV enables the adaptive guardbanding technique to adapt the frequency simultaneously for dynamic voltage and temperature variations, as well as the sequence of instructions. The proposed technique achieves average 1.6× speedup for error-intolerant applications compared to recent work [33]. The proposed technique has 0.022% area overhead, and imposes only 0.034% and 0.031% total power overhead for intolerant and probabilistic applications respectively.