Predictive TCAD Approach for the Analysis of Hot-Carrier-Stress Degradation in Integrated STI-based LDMOS Transistors

A physically-based approach suitable for TCAD analyses has been developed for the hot-carrier-stress (HCS) degradation prediction in lateral DMOS transistors with shallow trench isolation (STI). The measured linear drain current degradation induced by HCS is nicely reproduced by TCAD results for different LDMOS devices at significant stress conditions on an extended range of stress times and current drifts. A quantitative understanding of the generation kinetics and spatial distribution of the interface-trap concentration (Nit) along the Si/SiO2 interface is obtained. TCAD results confirmed that interface traps are mainly formed at the STI corner, where the use of the charge-pumping technique fails due to the thickness of the STI oxide which limits the effects of the applied gate biases.