In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead and cache memory access time for different codeword sizes and code-segment sizes, as well as their correction ability as a function of codeword/codesegment sizes. We show the different trade-offs that can be achieved in terms of impact on area overhead, performance and correction ability, thus giving insight to designers for the selection of the optimal ECC and codeword organization/codesegment size for a given application.
Error correcting code analysis for cache memory high reliability and performance / D. Rossi; N. Timoncini; M. Spica; C. Metra. - ELETTRONICO. - (2011), pp. 1-6. (Intervento presentato al convegno Design, Automation and Test in Europe Conference and Exhibition (DATE 2011) tenutosi a Grenoble, France nel 14-18 marzo 2011) [10.1109/DATE.2011.5763257].
Error correcting code analysis for cache memory high reliability and performance
ROSSI, DANIELE;METRA, CECILIA
2011
Abstract
In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead and cache memory access time for different codeword sizes and code-segment sizes, as well as their correction ability as a function of codeword/codesegment sizes. We show the different trade-offs that can be achieved in terms of impact on area overhead, performance and correction ability, thus giving insight to designers for the selection of the optimal ECC and codeword organization/codesegment size for a given application.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
