This study presents vertical Si-nanowire (SiNW) gate-all-around (GAA) non-volatile memory with channel diameter down to 20nm. The junctionless devices with SiN trap layer is found to have comparable memory characteristics (3.2V in 1ms P/E at +15V/-16V) to the junction-based cell. Despite of that, the absence of junctions reduces the process complexity and makes vertical SiNW a suitable platform for multi-level stacked ultra high density memory application.

Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application

GNANI, ELENA;BACCARANI, GIORGIO;
2011

Abstract

This study presents vertical Si-nanowire (SiNW) gate-all-around (GAA) non-volatile memory with channel diameter down to 20nm. The junctionless devices with SiN trap layer is found to have comparable memory characteristics (3.2V in 1ms P/E at +15V/-16V) to the junction-based cell. Despite of that, the absence of junctions reduces the process complexity and makes vertical SiNW a suitable platform for multi-level stacked ultra high density memory application.
3rd IEEE International Memory Workshop
1
4
Y. Sun; H.Y. Yu; N. Singh; E. Gnani; G. Baccarani; K.C. Leong; G.Q. Lo; D.L. Kwong
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/106878
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