This study presents vertical Si-nanowire (SiNW) gate-all-around (GAA) non-volatile memory with channel diameter down to 20nm. The junctionless devices with SiN trap layer is found to have comparable memory characteristics (3.2V in 1ms P/E at +15V/-16V) to the junction-based cell. Despite of that, the absence of junctions reduces the process complexity and makes vertical SiNW a suitable platform for multi-level stacked ultra high density memory application.
Y. Sun, H.Y. Yu, N. Singh, E. Gnani, G. Baccarani, K.C. Leong, et al. (2011). Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application. MONTEREY CA : IEEE [10.1109/IMW.2011.5873187].
Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application
GNANI, ELENA;BACCARANI, GIORGIO;
2011
Abstract
This study presents vertical Si-nanowire (SiNW) gate-all-around (GAA) non-volatile memory with channel diameter down to 20nm. The junctionless devices with SiN trap layer is found to have comparable memory characteristics (3.2V in 1ms P/E at +15V/-16V) to the junction-based cell. Despite of that, the absence of junctions reduces the process complexity and makes vertical SiNW a suitable platform for multi-level stacked ultra high density memory application.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
