This paper presents vertical Si-nanowire (SiNW) gate-all-around nonvolatile memory (NVM) devices of two different kinds: junction based and junctionless (JL). Si nanocrystals (SiNCs) and silicon nitride (SiN) are used as trap layers. The devices are fabricated using complementary-metal-oxide-semiconductor compatible top-down process technology and compared on the bases of improved performance and reduced process complexity. The junction-based 50-nm vertical SiNW memory device with a SiNC trap layer shows significant performance improvements on program/erase (P/E) speed and windows (3.5 V in 1-ms P/E at +15/-16 V) over a memory cell with a SiN trap layer (1.3 V in 1-ms P/E at +15/-16 V). On the other hand, the JL device with a SiN trap layer, realized on a highly scaled SiNW channel down to 20 nm, is found to have comparable memory characteristics (3.2 V in 1-ms P/E at +15/-16 V) to a corresponding 20-nm SiNW junction-based cell (3.2 V in 1-ms P/E at +15/-16 V). Despite that, the absence of junctions reduces process complexity and makes a vertical SiNW a suitable platform for multilevel stacked ultra-high density memory applications.
Vertical-Si-Nanowire-Based Nonvolatile Memory Devices With Improved Performance and Reduced Process Complexity
GNANI, ELENA;BACCARANI, GIORGIO;
2011
Abstract
This paper presents vertical Si-nanowire (SiNW) gate-all-around nonvolatile memory (NVM) devices of two different kinds: junction based and junctionless (JL). Si nanocrystals (SiNCs) and silicon nitride (SiN) are used as trap layers. The devices are fabricated using complementary-metal-oxide-semiconductor compatible top-down process technology and compared on the bases of improved performance and reduced process complexity. The junction-based 50-nm vertical SiNW memory device with a SiNC trap layer shows significant performance improvements on program/erase (P/E) speed and windows (3.5 V in 1-ms P/E at +15/-16 V) over a memory cell with a SiN trap layer (1.3 V in 1-ms P/E at +15/-16 V). On the other hand, the JL device with a SiN trap layer, realized on a highly scaled SiNW channel down to 20 nm, is found to have comparable memory characteristics (3.2 V in 1-ms P/E at +15/-16 V) to a corresponding 20-nm SiNW junction-based cell (3.2 V in 1-ms P/E at +15/-16 V). Despite that, the absence of junctions reduces process complexity and makes a vertical SiNW a suitable platform for multilevel stacked ultra-high density memory applications.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
