Risks of Silent Data Corruption Due to the Combined Effects of Latent Faults and Aging Phenomena Affecting FinFET-Based ICs

We analyzed the effect of faults and aging phenomena possibly affecting circuits implemented by FinFET technology. We considered the occurrence of stuck-on and stuck-open faults on one or more fins of FinFETs, which have been proven to be the most likely faults. When the number of faulty fins is low, such faults may be not detected during manufacturing test, thus remaining present as “latent” faults in chips that are put into the market. Therefore, during circuit operation in the field, such latent faults could combine with aging mechanisms, such as Bias Temperature Instability (BTI). We performed electrical level simulations to analyze the effects due to the simultaneous presence of such latent faults and BTI. We found that it may cause an increase in circuit’s delay that is higher than the sum of the delay increase due to latent faults only, and BTI only. As an example, for one of the circuits considered in this paper as a case study, we observed that the presence of latent faults and BTI induces a delay increase of the 34.8%, while the presence of latent faults only causes a delay increase of the 11%, and BTI only a delay increase of the 9.7%. We also found that circuits’ delay may consequently exceed their time margins after only a few months of operation in the field, possibly resulting in silent data corruption, with consequent risks for circuit’s reliability.