Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs

Editor's notes: This keynote article presents a comprehensive and impactful contribution to energy-efficient TinyML through the design of domain-specific RISC-V instruction set architecture (ISA) extensions for Edge AI workloads. The authors provide detailed hardware-software codesign contributions, including sub-byte SIMD arithmetic, fused mac-load operations, and vector lockstep execution within tightly coupled compute clusters. This keynote exemplifies the potential of open ISAs and specialized microarchitectures to advance the next generation of TinyML and Edge AI systems. - Theocharis Theocharides, University of Cyprus, Cyprus - Marian Verhelst, KU Leuven, Belgium - Vijay Janapa Reddy, Harvard University, USA - Evgeni Gousev, Qualcomm, USA