The widespread diffusion of compute-intensive edge-AI workloads and the stringent demands of modern autonomous systems require advanced heterogeneous embedded architectures. Such architectures must support high-performance and reliable execution of parallel tasks with different levels of criticality. Hardware-assisted virtualization is crucial for isolating applications concurrently executing these tasks under real-time constraints, but interrupt virtualization poses challenges in ensuring transparency to virtual guests while maintaining real-time system features, such as interrupt vectoring, nesting, and tail-chaining. Despite its rapid advancement to address virtualization needs for mixed-criticality systems, the RISC-V ecosystem still lacks interrupt controllers with integrated virtualization and real-time features, currently relying on non-deterministic, bus-mediated message-signaled interrupts (MSIs) for virtualization. To overcome this limitation, we present the design, implementation, and in-system assessment of vCLIC, a virtualization extension to the RISC-V CLIC fast interrupt controller. Our approach achieves 20 x interrupt latency speedup over the software emulation required for handling non-virtualization-aware systems, reduces response latency by 15% compared to existing MSI- based approaches, and is free from interference from the system bus, at an area cost of just 8kGE when synthesized in an advanced 16nm FinFet technology
Zelioli, E., Ottaviano, A., Balas, R., Wistoff, N., Garofalo, A., Benini, L. (2024). vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems. Institute of Electrical and Electronics Engineers Inc. [10.1109/iccd63220.2024.00051].
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems
Garofalo, Angelo;Benini, Luca
2024
Abstract
The widespread diffusion of compute-intensive edge-AI workloads and the stringent demands of modern autonomous systems require advanced heterogeneous embedded architectures. Such architectures must support high-performance and reliable execution of parallel tasks with different levels of criticality. Hardware-assisted virtualization is crucial for isolating applications concurrently executing these tasks under real-time constraints, but interrupt virtualization poses challenges in ensuring transparency to virtual guests while maintaining real-time system features, such as interrupt vectoring, nesting, and tail-chaining. Despite its rapid advancement to address virtualization needs for mixed-criticality systems, the RISC-V ecosystem still lacks interrupt controllers with integrated virtualization and real-time features, currently relying on non-deterministic, bus-mediated message-signaled interrupts (MSIs) for virtualization. To overcome this limitation, we present the design, implementation, and in-system assessment of vCLIC, a virtualization extension to the RISC-V CLIC fast interrupt controller. Our approach achieves 20 x interrupt latency speedup over the software emulation required for handling non-virtualization-aware systems, reduces response latency by 15% compared to existing MSI- based approaches, and is free from interference from the system bus, at an area cost of just 8kGE when synthesized in an advanced 16nm FinFet technologyI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.