A memory interface for a 3D System-on-a-Chip based on capacitive coupling is implemented in 90nm CMOS technology. The design choices have been driven by an innovative 3D extraction and simulation flow. The presented work exploits AC capacitive coupling for chip-to-chip communication running up to 250MHz. The interface transfers 128 bit words between stacked SRAMs in an ARM-based System-on-a-Chip (SoC). The 3D memory interface achieves a total throughput of 32Gbit/sec with an average energy consumption of 35uW/Gbit/sec and an area occupancy of 0.05mm square.
M. Scandiuzzo, R. Cardu, S. Cani, S. Spolzino, L. Perugini, E. Franchi Scarselli, et al. (2010). 3D System on chip memory interface based on modeled capacitive coupling interconnections. s.l : s.n [10.1109/3DIC.2010.5751459].
3D System on chip memory interface based on modeled capacitive coupling interconnections
PERUGINI, LUCA;FRANCHI SCARSELLI, ELEONORA;GUERRIERI, ROBERTO
2010
Abstract
A memory interface for a 3D System-on-a-Chip based on capacitive coupling is implemented in 90nm CMOS technology. The design choices have been driven by an innovative 3D extraction and simulation flow. The presented work exploits AC capacitive coupling for chip-to-chip communication running up to 250MHz. The interface transfers 128 bit words between stacked SRAMs in an ARM-based System-on-a-Chip (SoC). The 3D memory interface achieves a total throughput of 32Gbit/sec with an average energy consumption of 35uW/Gbit/sec and an area occupancy of 0.05mm square.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
