CRIS Current Research Information System
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishLatest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowires, etc.) have deployed bottom-that reach feature sizes well below 65nm, holding great promise for future large silicon-based integrated circuits. However, intrinsically have much higher failure rates than CMOS-based ones. Thus, new design methodologies must address the combination device-level error-prone technologies with system integration constraints (low power, performance) to deliver competitive nanometer scale. In this paper we show that a very promising way to achieve nano-scale devices is combining imperfection-techniques during fabrication with gate defect modeling at circuit level. Our results using this approach to define a Carbon Transistor (CNFET)-based design flow for nanoscale logic circuits attain more than 3Ã energy-delay-product advantage compared CMOS-based ones.
| Titolo: | System-Level Design for Nano-Electronics | |
| Autore/i: | Atienza D.; Bobba S. K.; Poli M.; De Micheli G.; BENINI, LUCA | |
| Autore/i Unibo: | ||
| Anno: | 2007 | |
| Titolo del libro: | Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on | |
| Pagina iniziale: | 747 | |
| Pagina finale: | 751 | |
| Abstract: | Latest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowires, etc.) have deployed bottom-that reach feature sizes well below 65nm, holding great promise for future large silicon-based integrated circuits. However, intrinsically have much higher failure rates than CMOS-based ones. Thus, new design methodologies must address the combination device-level error-prone technologies with system integration constraints (low power, performance) to deliver competitive nanometer scale. In this paper we show that a very promising way to achieve nano-scale devices is combining imperfection-techniques during fabrication with gate defect modeling at circuit level. Our results using this approach to define a Carbon Transistor (CNFET)-based design flow for nanoscale logic circuits attain more than 3Ã energy-delay-product advantage compared CMOS-based ones. | |
| Data prodotto definitivo in UGOV: | 3-feb-2011 | |
| Appare nelle tipologie: | 4.01 Contributo in Atti di convegno |
File in questo prodotto:
Copyright © 2022