Latest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowires, etc.) have deployed bottom-that reach feature sizes well below 65nm, holding great promise for future large silicon-based integrated circuits. However, intrinsically have much higher failure rates than CMOS-based ones. Thus, new design methodologies must address the combination device-level error-prone technologies with system integration constraints (low power, performance) to deliver competitive nanometer scale. In this paper we show that a very promising way to achieve nano-scale devices is combining imperfection-techniques during fabrication with gate defect modeling at circuit level. Our results using this approach to define a Carbon Transistor (CNFET)-based design flow for nanoscale logic circuits attain more than 3Ã energy-delay-product advantage compared CMOS-based ones.