Multicore architectures will be adopted in the sub-50nm CMOS technology nodes for virtually all application domains with energy efficiency requirements exceeding 10GOPS/Watt. Unfortunately, future technology nodes will be increasingly affected by variation phenomena, and multicore architectures will be impacted in many ways by the variability of the underlying silicon fabrics [1, 6, 8]. Our architectural target is an advanced prototype of an industrial multicore platform for post-2014 set-top-box products, featuring a single CPU coordinator and an array of programmable VLIWhardware accelerators with multi-threading support. Next-generation set-top-boxes will support very high resolution, high-frame rate video rendering with complex 3D GUIs and stereoscopic visualization support [2]. These applications require extensive image processing and enhancements functions which are embarrassingly parallel and will be distributed on the VLIW accelerator array as a large number of barrier-synchronized tasks. Accelerators are nominally homogeneous, but unfortunately variability causes significant perturbations on their performance and power consumption. We define a two-phase approach based on linear programming and bin packing. Thanks to these steps, the technique performs task allocation exploiting the awareness of performance and power variations of the cores, thus minimizing deadline misses and improving energy efficiency of the platform with respect to a variation-blind approach. In this work we consider variability effects acting independently on critical path delay, leakage power, and dynamic power [3]. Variability distribution data have been obtained through the VAM tool [7]. This distribution is used to generate variability affected platforms.

Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints

PATERNA, FRANCESCO;A. Acquaviva;BENINI, LUCA
2010

Abstract

Multicore architectures will be adopted in the sub-50nm CMOS technology nodes for virtually all application domains with energy efficiency requirements exceeding 10GOPS/Watt. Unfortunately, future technology nodes will be increasingly affected by variation phenomena, and multicore architectures will be impacted in many ways by the variability of the underlying silicon fabrics [1, 6, 8]. Our architectural target is an advanced prototype of an industrial multicore platform for post-2014 set-top-box products, featuring a single CPU coordinator and an array of programmable VLIWhardware accelerators with multi-threading support. Next-generation set-top-boxes will support very high resolution, high-frame rate video rendering with complex 3D GUIs and stereoscopic visualization support [2]. These applications require extensive image processing and enhancements functions which are embarrassingly parallel and will be distributed on the VLIW accelerator array as a large number of barrier-synchronized tasks. Accelerators are nominally homogeneous, but unfortunately variability causes significant perturbations on their performance and power consumption. We define a two-phase approach based on linear programming and bin packing. Thanks to these steps, the technique performs task allocation exploiting the awareness of performance and power variations of the cores, thus minimizing deadline misses and improving energy efficiency of the platform with respect to a variation-blind approach. In this work we consider variability effects acting independently on critical path delay, leakage power, and dynamic power [3]. Variability distribution data have been obtained through the VAM tool [7]. This distribution is used to generate variability affected platforms.
CF '10 Proceedings of the 7th ACM international conference on Computing frontiers
109
110
F. Paterna; A. Acquaviva; A. Caprara; F. Papariello; G. Desoli; L. Benini
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/95993
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