One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced single event upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency.

Rogenmoser, M., Benini, L. (2023). Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm [10.1109/ICECS58634.2023.10382727].

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Benini, Luca
2023

Abstract

One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced single event upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency.
2023
2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
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Rogenmoser, M., Benini, L. (2023). Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm [10.1109/ICECS58634.2023.10382727].
Rogenmoser, Michael; Benini, Luca
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/958749
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