Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.
Raghav S. , Ruggiero M. , Atienza D. , Pinto C. , Marongiu A. , Benini L. (2010). Scalable instruction set simulator for thousand-core architectures running on GPGPUs. NEW YORK : IEEE Press.
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
PINTO, CHRISTIAN;MARONGIU, ANDREA;BENINI, LUCA
2010
Abstract
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
