Three-dimensional integrated circuits, where multiple silicon layers are stacked vertically have emerged recently. The3DICs have smaller form factor, shorter and efficient use of wires and allow integration of diverse technologies in the same device. The use of Networks on Chips (NoCs) to connect components in a 3D chip is a necessity. In this short paper, we present an outline on designing application-specific NoCs for 3D ICs.
Design of Networks on Chips for 3D ICs / Murali S.; Benini L.; De Micheli G.. - STAMPA. - (2010), pp. 167-168. (Intervento presentato al convegno Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific tenutosi a Taipei nel 18-21 Jan. 2010) [10.1109/ASPDAC.2010.5419902].
Design of Networks on Chips for 3D ICs
BENINI, LUCA;
2010
Abstract
Three-dimensional integrated circuits, where multiple silicon layers are stacked vertically have emerged recently. The3DICs have smaller form factor, shorter and efficient use of wires and allow integration of diverse technologies in the same device. The use of Networks on Chips (NoCs) to connect components in a 3D chip is a necessity. In this short paper, we present an outline on designing application-specific NoCs for 3D ICs.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
