This paper describes a System on Chip implementation of a reconfigurable digital signal processor. The device is suitable for execution of a wide range of applications exploiting a balanced mix of heterogeneous reconfigurable fabrics merged together by a flexible and efficient communication infrastructure based on a 64-bit Network On Chip. The SoC combines a fine grain embedded FPGA, a mid grain configurable processor and a coarse grain reconfigurable array. An ARM processor featuring a resident operating system is the SoC supervisor, managing communication, synchronization and reconfiguration mechanisms. This computational model enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigurable engines. The SoC has been fabricated in 90-nm technology, the die area being 110mm2

A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing / D. Rossi; F. Campi; S. Spolzino; S. Pucillo; R. Guerrieri. - In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. - ISSN 0018-9200. - STAMPA. - 45, n.8:(2010), pp. 1615-1626. [10.1109/JSSC.2010.2048149]

A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing

ROSSI, DAVIDE;CAMPI, FABIO;GUERRIERI, ROBERTO
2010

Abstract

This paper describes a System on Chip implementation of a reconfigurable digital signal processor. The device is suitable for execution of a wide range of applications exploiting a balanced mix of heterogeneous reconfigurable fabrics merged together by a flexible and efficient communication infrastructure based on a 64-bit Network On Chip. The SoC combines a fine grain embedded FPGA, a mid grain configurable processor and a coarse grain reconfigurable array. An ARM processor featuring a resident operating system is the SoC supervisor, managing communication, synchronization and reconfiguration mechanisms. This computational model enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigurable engines. The SoC has been fabricated in 90-nm technology, the die area being 110mm2
2010
A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing / D. Rossi; F. Campi; S. Spolzino; S. Pucillo; R. Guerrieri. - In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. - ISSN 0018-9200. - STAMPA. - 45, n.8:(2010), pp. 1615-1626. [10.1109/JSSC.2010.2048149]
D. Rossi; F. Campi; S. Spolzino; S. Pucillo; R. Guerrieri
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/92609
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