Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips, like the Arm SVE-based Fujitsu A64FX, powering the TOP500 leader Fugaku. The RISC-V V extension has recently reached 1.0-Frozen status. Here, we present its first open-source implementation, discuss the new specification's impact on the micro-architecture of a lane-based design, and provide insights on performance-oriented design of coupled scalar-vector processors. Our system achieves comparable/better PPA than state-of-the-art vector engines that implement older RVV versions: 15% better area, 6% improved throughput, and FPU utilization >98.5% on crucial kernels.

A 'New Ara' for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design / Perotti M.; Cavalcante M.; Wistoff N.; Andri R.; Cavigelli L.; Benini L.. - ELETTRONICO. - 2022-July:(2022), pp. 43-51. (Intervento presentato al convegno 2022 IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP) tenutosi a Gothenburg, Sweden nel 12-14 July 2022) [10.1109/ASAP54787.2022.00017].

A 'New Ara' for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design

Benini L.
2022

Abstract

Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips, like the Arm SVE-based Fujitsu A64FX, powering the TOP500 leader Fugaku. The RISC-V V extension has recently reached 1.0-Frozen status. Here, we present its first open-source implementation, discuss the new specification's impact on the micro-architecture of a lane-based design, and provide insights on performance-oriented design of coupled scalar-vector processors. Our system achieves comparable/better PPA than state-of-the-art vector engines that implement older RVV versions: 15% better area, 6% improved throughput, and FPU utilization >98.5% on crucial kernels.
2022
2022 IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)
43
51
A 'New Ara' for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design / Perotti M.; Cavalcante M.; Wistoff N.; Andri R.; Cavigelli L.; Benini L.. - ELETTRONICO. - 2022-July:(2022), pp. 43-51. (Intervento presentato al convegno 2022 IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP) tenutosi a Gothenburg, Sweden nel 12-14 July 2022) [10.1109/ASAP54787.2022.00017].
Perotti M.; Cavalcante M.; Wistoff N.; Andri R.; Cavigelli L.; Benini L.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/907419
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