Hierarchical very-large-scale integration (VLSI) flows are an understudied yet critical approach to achieving design closure at giga-scale complexity and gigahertz frequency targets. This paper proposes a novel hierarchical physical design flow enabling the building of high-density and commercial-quality two-tier face-to-face-bonded hierarchical 3D ICs. We significantly reduce the associated manufacturing cost compared to existing 3D implementation flows and, for the first time, achieve cost competitiveness against the 2D reference in large modern designs. Experimental results on complex industrial and open manycore processors demonstrate in two advanced nodes that the proposed flow provides major power, performance, and area/cost (PPAC) improvements of 1.2 to 2.2 × compared with 2D, where all metrics are improved simultaneously, including up to power savings.
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs / Agnesina A.; Brunion M.; Garcia-Ortiz A.; Catthoor F.; Milojevic D.; Komalan M.; Cavalcante M.; Riedel S.; Benini L.; Lim S.K.. - ELETTRONICO. - (2022), pp. 1-6. (Intervento presentato al convegno ISLPED '22: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design tenutosi a Boston MA USA nel 1-3 August) [10.1145/3531437.3539702].
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs
Benini L.;
2022
Abstract
Hierarchical very-large-scale integration (VLSI) flows are an understudied yet critical approach to achieving design closure at giga-scale complexity and gigahertz frequency targets. This paper proposes a novel hierarchical physical design flow enabling the building of high-density and commercial-quality two-tier face-to-face-bonded hierarchical 3D ICs. We significantly reduce the associated manufacturing cost compared to existing 3D implementation flows and, for the first time, achieve cost competitiveness against the 2D reference in large modern designs. Experimental results on complex industrial and open manycore processors demonstrate in two advanced nodes that the proposed flow provides major power, performance, and area/cost (PPAC) improvements of 1.2 to 2.2 × compared with 2D, where all metrics are improved simultaneously, including up to power savings.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
