Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64- kB GC-eDRAM macro was fabricated in a 65- nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 mu s retention time.

64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique / Harel, O; Casarrubias, EN; Eggimann, M; Gurkaynak, F; Benini, L; Teman, A; Giterman, R; Burg, A. - In: IEEE SOLID-STATE CIRCUITS LETTERS. - ISSN 2573-9603. - ELETTRONICO. - 5:(2022), pp. 170-173. [10.1109/LSSC.2022.3182531]

64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique

Benini, L;Burg, A
2022

Abstract

Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64- kB GC-eDRAM macro was fabricated in a 65- nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 mu s retention time.
2022
64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique / Harel, O; Casarrubias, EN; Eggimann, M; Gurkaynak, F; Benini, L; Teman, A; Giterman, R; Burg, A. - In: IEEE SOLID-STATE CIRCUITS LETTERS. - ISSN 2573-9603. - ELETTRONICO. - 5:(2022), pp. 170-173. [10.1109/LSSC.2022.3182531]
Harel, O; Casarrubias, EN; Eggimann, M; Gurkaynak, F; Benini, L; Teman, A; Giterman, R; Burg, A
File in questo prodotto:
Eventuali allegati, non sono esposti

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/904922
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? 1
social impact