Many computer vision applications require fast and accurate 3D measurements. However, despite the advent of powerful computing architectures (e.g., multicore CPU and GPU), most top-ranked dense stereo algorithms rely on global 2D disparity optimization methods that are often too slow for practical use. Moreover, their huge memory requirements are typically not suited to devices with constrained resources (e.g., FPGA). Nevertheless, algorithms based on 1D disparity optimization methods (ı.e., Dynamic Programming and Scanline Optimization) provide a good trade-off between accuracy and efficiency with a limited memory footprint. In this paper, we show that enforcing a relaxed local consistency constraint to the disparity fields, provided by fast 1D disparity optimization methods, yields much more rapidly, results comparable to those of the top ranked approaches. The simple and non-iterative computational structure of our proposal enables us to exploit coarse grained parallelism on multicore CPUs. Moreover, due to its limited memory footprint, our proposal could be potentially mapped on devices, such as FPGA, with constrained resources.

Fast locally consistent dense stereo on multicore

MATTOCCIA, STEFANO
2010

Abstract

Many computer vision applications require fast and accurate 3D measurements. However, despite the advent of powerful computing architectures (e.g., multicore CPU and GPU), most top-ranked dense stereo algorithms rely on global 2D disparity optimization methods that are often too slow for practical use. Moreover, their huge memory requirements are typically not suited to devices with constrained resources (e.g., FPGA). Nevertheless, algorithms based on 1D disparity optimization methods (ı.e., Dynamic Programming and Scanline Optimization) provide a good trade-off between accuracy and efficiency with a limited memory footprint. In this paper, we show that enforcing a relaxed local consistency constraint to the disparity fields, provided by fast 1D disparity optimization methods, yields much more rapidly, results comparable to those of the top ranked approaches. The simple and non-iterative computational structure of our proposal enables us to exploit coarse grained parallelism on multicore CPUs. Moreover, due to its limited memory footprint, our proposal could be potentially mapped on devices, such as FPGA, with constrained resources.
2010
Computer Vision and Pattern Recognition Workshops (CVPRW), 2010 IEEE Computer Society Conference on
69
76
S. Mattoccia
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/89231
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